John H Lau, Unimicron Technology Corporation
Directions for connecting with the WebEx stream will be sent via email to all registrants 24-hours, and 15 minutes prior to the event.
11:50 AM – 12:00 PM: On-site check-in
12:00 PM: Presentation & QA
WE USUALLY GET the PRESENTER’S SLIDE DECK, but sometimes not. When the speaker provides it, in original or sanitized form, it will be uploaded to the chapter website – www.ieee.org/scveps. Older presentations may also be accessed on the same page.
Summary:
Chiplet is a chip design method and heterogeneous integration (HI) is a chip packaging method. HI uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (either side-by-side, stacked, or both) with different sizes and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem on a common package substrate. These chips can be any kind of devices and don’t have to be chiplets. On the other hand, for chiplets, they have to use the heterogeneous integration to package them. For the next few years, we will see more implementations of a higher level of chiplet designs and HI packaging, whether it is for time-to-market, performance, form factor, power consumption or cost. In this lecture, the introduction, recent advances, and trends in chiplet design and HI packaging will be presented.
Talk Outline:
Introduction; System-on-Chip (SoC); Chiplet Design and HI Packaging; AMD Chiplet Design (EPYZ and RYZEN); Intel Chiplet Design (FOVEROS, FOVEROS Direct, and Ponte Vecchio; TSMC chiplet Design (SoIC, SoIC + CoWoS, SoIC + InFO PoP); Lateral Interconnects (Intel’s EMIB, IBM’s solution for EMIB, Applied Materials’ Bridge Embedded in Fan-Out EMC, SPIL’s FO-EB, TSMC’s LSI, ASE’s sFOCoS, IME’s EFI, Amkor’s S-Connect Fan-Out, and UCIe); HI Packaging on Organic Substrates:; HI Packaging on Silicon Substrates HI Packaging on Ceramic Substrate; Assembly Technologies for Chiplet Design and HI Packaging; Trends in Chiplet Design and HI Packaging.
Bio:
John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging and SMT assembly, has published more than 515 peer-reviewed papers (of which 370 as the principal investigator), 40 issued and pending US patents (of which 25 as the principal inventor), and 23 textbooks (all as the first author). John has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.
— SoC, AMD, Intel, TSMC, IBM, interposer, substrates, attach, assembly, trends …