Rajendra (Raj) Pendse, Director of Si Packaging, Meta Reality Labs
Directions for connecting with the WebEx stream will be sent via email to all registrants 24-hours, and 15 minutes prior to the event.
11:30 – 11:45 AM: Arrive at SEMI Hdqtrs, lunch provided (for on-site attendees)
11:50 AM – 12:00 PM: On-line check-in
12:00 PM: Presentation & QA
WE USUALLY GET the PRESENTER’S SLIDE DECK, but sometimes not. When the speaker provides it, in original or update form, it will be uploaded to the chapter website – www.ieee.org/scveps. Older presentations may also be accessed on the same page.
Summary: This presentation will focus on the new trajectory for Si Packaging technology set by the emergence of AR/VR hardware and advanced wearable computing. We believe the next major step beyond handheld computing will be wearable computing in the form of novel, hands-off and all-day wearable AR/VR devices like AR glasses. These devices will continue the remarkable journey of miniaturization and power/performance carved out by its predecessors.
We will discuss the complex array of Si and packaging technologies that lie “under the hood” of such devices, spanning these three areas: Augmented Reality Processing (ARP), Display and Imaging (D&I), and Low-energy Wireless (LW) communication. We will demonstrate unique approaches that combine advanced packaging technologies like flip chip, fan-out wafer-level packaging and TSVs, often within the same package. Finally, we will discuss the challenges created by the need to spawn new ecosystems such as heterogeneous integration and fabrication methods that often fall in the grey zone between Foundry and OSAT.
Bio: Dr. Rajendra (Raj) Pendse is Director of Si Packaging at Meta Reality Labs and leads the development of advanced Si/Packaging solutions for AR/VR hardware. Raj was previously Vice President of Package Engineering at Qualcomm and played various leadership roles in Package development at STATS ChipPAC, Hewlett-Packard Labs and National Semiconductor. Raj’s work throughout his career spans the gamut from packaging of microprocessors, ASIC’s and GPU’s for High Performance Computing to packaging solutions for Logic and Analog devices that find use in mobile platforms and consumer hardware. His most recent focus has been in 3D and Wafer Level Packaging for AR/VR hardware.
Raj completed his BS in Materials Science from IIT Bombay with Top in Class honors and his Doctorate in Materials Science from UC Berkeley.
